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教师主页 团队成员 科研项目 研究领域 学术成果 教学 科研分享 新闻动态 疼痛医学中心 成果介绍 软件 毕业去向 加入我们 联系我们 安丰伟 Google Scholar ResearcherID 副教授 深港微电子学院 安丰伟博士于2019年加入南方科技大学，2013年在日本广岛大学获得工学博士学位。现在担任南方科技大学深港微电子学院副教授。在此之前担任过日本松下半导体公司的主管工程师及日本广岛大学副教授，其专长是图像识别与机器学习的大规模数字集成电路设计。积累了十年以上图像处理、图像识别、机器学习的电路设计和系统集成（SoC）等经验，具有丰富的学术界和工业界的背景。安教授在松下半导体公司开发的产品和在广岛大学的研究成果等的目标应用是高级辅助驾驶系统（ADAS）和自动驾驶。团队目前继续从事面向自动驾驶的动态目标追踪专用芯片的研究。 个人简介 个人简介 研究领域 安丰伟博士的主要研究领域是基于计算机视觉的低功耗边缘人工智能芯片设计，具体包括图像处理、图像识别、机器学习的超大规模数字集成电路设计和系统集成，并有在工业界的研究开发经验。 教学 片上系统集成电路设计 学术成果 查看更多 2022： 论文： Dong, P., Chen, Z., Li, Z., …Wang, C., An, F., Configurable Image Rectification and Disparity Refinement for Stereo Vision, IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(10), pp. 3973–3977 Yao, R., Chen, L., Dong, P., Chen, Z., An, F., A Compact Hardware Architecture for Bilateral Filter with the Combination of Approximate Computing and Look-Up Table, IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(7), pp. 3324–3328 Liang, Z., Chen, L., An, F., 3D Vehicle Surround View Algorithm for Embedded Platform, Journal of Physics: Conference Series, 2022, 2253(1), 012026 Lyu, H., An, F., Zhao, S., Mao, W., Yu, H., A 703.4-GOPs/W Binary SegNet Processor with Computing-Near-Memory Architecture for Road Detection, IEEE Design and Test, 2022, 39(2), pp. 74–83 Luo, Y., Li, P., Shi, G., …Chen, L., An, F., Lane Departure Assessment via Enhanced Single Lane-Marking, Sensors, 2022, 22(5), 2024 Tan, Y., Deng, H., Sun, M., …Wang, C., An, F., A Reconfigurable Coprocessor for Simultaneous Localization and Mapping Algorithms in FPGA, IEEE Transactions on Circuits and Systems II: Express Briefs, 2022 Xiao, L., Chen, L., An, F., An 11.6aF/kPa Mechanical Stress Sensor with 0.808% Temperature-drift Oscillator for Flip-chip Packaging, IEEE Transactions on Circuits and Systems II: Express Briefs, 2022 Dong, P., Chen, Z., Li, Z., …Chen, L., An, F., A 4.29nJ/pixel Stereo Depth Coprocessor with Pixel Level Pipeline and Region Optimized Semi-Global Matching for IoT Application, IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(1), pp. 334–346   2021: 论文： Liu, F., Wang, J., Liu, B., …An, F., Wang, C., Low computation and high efficiency sobel edge detector for robot vision, 2021 IEEE International Conference on Real-Time Computing and Robotics, RCAR 2021, 2021, pp. 684–689 Chen, Z., Dong, P., Li, Z., …Chen, L., An, F., Real-Time FPGA-Based Binocular Stereo Vision System with Semi-Global Matching Algorithm, International System on Chip Conference, 2021, 2021-September, pp. 158–163 Zhang, Y., Peng, Z., Yao, R., …Chen, L., An, F., Efficient VLSI Architecture for Edge Sensing Anti-Aliasing Demosaicing, 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2021, 2021, pp. 105–106 Yao, R., Deng, H., Zhang, W., …Chen, L., An, F., A Pseudo 943 million Frames per Rate High-Speed Camera with Asynchronous Double-Frame Exposure for Motion Estimation, 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2021, 2021, pp. 103–104 Wang, J., Zhan, Y., Wang, Z., …Wang, C., Zou, X., A Reconfigurable Matrix Multiplication Coprocessor with High Area and Energy Efficiency for Visual Intelligent and Autonomous Mobile Robots, Proceedings – A-SSCC 2021: IEEE Asian Solid-State Circuits Conference, 2021 Dong, P., Li, Z., Chen, Z., …Wang, C., An, F., A 139 fps pixel-level pipelined binocular stereo vision accelerator with region-optimized semi-global matching, Proceedings – A-SSCC 2021: IEEE Asian Solid-State Circuits Conference, 2021 专利： 一种高速低资源消耗的视差优化方法、装置及终端，中国发明专利，2021-12-1 基于raw数据进行边缘检测的去马赛克方法及电路，中国发明专利，2021-12-06 一种双边滤波器的硬件架构系统及其权重优化方法，中国发明专利，2021-11-30 一种适用于混合精度神经网络的定点乘加运算单元及方法，中国发明专利，2021-02-09 一种低功耗立体匹配系统及获取深度信息的方法，PCT，2021-03-29 一种适用于混合精度神经网络的定点乘加运算单元及方法，PCT，2021-11-19   2020: 论文： Deng, H., Dong, P., Li, Z., …Luo, Y., An, F., Robot navigation based on pseudo-binocular stereo vision and linear fitting, Proceedings of 2020 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2020, 2020, pp. 174–175, 9332014 Zhan, Y., Wang, Z., Xu, J., …Chi, W., Wang, C., Fast CORDIC based Generalized-Voronoi-Diagram Hardware Accelerator for Efficient Robotic Exploration, 2020 5th International Conference on Robotics and Automation Engineering, ICRAE 2020, 2020, pp. 100–105, 9310864 Xu, C., Peng, Z., Hu, X., …Chen, L., An, F., FPGA-Based Low-Visibility Enhancement Accelerator for Video Sequence by Adaptive Histogram Equalization with Dynamic Clip-Threshold, IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67(11), pp. 3954–3964, 9151314 Mao, W., Xiao, Z., Xu, P., …An, F., Yu, H., Energy-efficient machine learning accelerator for binary neural networks, Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 2020, pp. 77–82 Xu, P., Xiao, Z., Wang, X., …Wang, C., An, F., A multi-core object detection coprocessor for multi-scale/type classification applicable to iot devices, Sensors (Switzerland), 2020, 20(21), pp. 1–13, 6239 Xiao, Z., Xu, P., Wang, X., Chen, L., An, F., A Multi-Class Objects Detection Coprocessor with Dual Feature Space and Weighted Softmax, IEEE Transactions on Circuits and Systems II: Express Briefs, 2020, 67(9), pp. 1629–1633, 9144541  专利： 面向运动估计的跨帧超高速相机设计方法及运动估计方法，中国发明专利，2020-11-26 一种运动阻碍型疾病诊断装置，中国发明专利，2020-10-19 一种低功耗立体匹配系统及获取深度信息的方法，中国发明专利，2020-07-31 一种相机标定方法、车道偏离预警方法及系统，中国发明专利，2020-06-15 一种脊柱侧弯检测模型的生成方法和计算机设备，中国发明专利，2020-03-12 一种脊柱侧弯检测模型的生成方法和计算机设备，PCT，2020-03-12   on/before2019： 论文： Zhao, S., An, F., Yu, H., A 307-fps 351.7-GOPs/W Deep Learning FPGA Accelerator for Real-Time Scene Text Recognition, Proceedings – 2019 International Conference on Field-Programmable Technology, ICFPT 2019, 2019, 2019-December, pp. 263–266, 8977892 An, F., Xu, P., Xiao, Z., Wang, C., FPGA-based object detection processor with HOG feature and SVM classifier, International System on Chip Conference, 2019, 2019-September, pp. 187–190, 9087991 Guan, J., An, F., Zhang, X., Chen, L., Mattausch, H.J., Energy-efficient hardware implementation of road-lane detection based on Hough transform with parallelized voting procedure and local maximum algorithm, IEICE Transactions on Information and Systems, 2019, E102D(6), pp. 1171–1182 Luo, A., An, F., Zhang, X., Mattausch, H.J., A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier, IEEE Access, 2019, 7, pp. 14472–14487, 8621001 An, F., Multi-port SRAM with Multi-bank for Self-organizing Maps Neural Network (Invited paper), 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 – Proceedings, 2018, 8564839 Zhang, X., An, F., Chen, L., Ishii, I., Mattausch, H.J., A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization, IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(10), pp. 3312–3325, 8301524 An, F., Zhang, X., Luo, A., Chen, L., Mattausch, H.J., A Hardware Architecture for Cell-Based Feature-Extraction and Classification Using Dual-Feature Space, IEEE Transactions on Circuits and Systems for Video Technology, 2018, 28(10), pp. 3086–3098, 7979565 Luo, A., An, F., Zhang, X., …Huang, Z., Mattausch, H.J., Flexible feature-space-construction architecture and its VLSI implementation for multi-scale object detection, Japanese Journal of Applied Physics, 2018, 57(4), 04FF04 Luo, A., An, F., Zhang, X., Chen, L., Mattausch, H.J., Resource-Efficient Object-Recognition Coprocessor with Parallel Processing of Multiple Scan Windows in 65-nm CMOS, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, 26(3), pp. 431–444 Huang, Z., Zhang, X., Chen, L., …Wang, H., Feng, S., A hardware-efficient vector quantizer based on self-organizing map for high-speed image compression, Applied Sciences (Switzerland), 2017, 7(11), 1106 Huang, Z., Zhang, X., Chen, L., …Wang, H., Feng, S., A vector-quantization compression circuit with on-chip learning ability for high-speed image sensor, IEEE Access, 2017, 5, pp. 22132–22143, 8070449 An, F., Zhang, X., Chen, L., Mattausch, H.J., Parallel-elementary-stream architecture for nearest-neighbor-search-based self-organizing map, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 – Proceedings, 2017, pp. 606–609, 7998991 Guan, J., An, F., Zhang, X., Chen, L., Mattausch, H.J., Parallelization of Hough transform for high-speed straight-line detection in XGA-size videos, 2017 IEEE International Conference on Consumer Electronics – Taiwan, ICCE-TW 2017, 2017, pp. 313–314, 7991121 An, F., Zhang, X., Chen, L., Ishii, I., Object-recognition VLSI for pedestrian detection in automotive applications, Proceedings of International Conference on ASIC, 2017, 2017-October, pp. 651–653 Luo, A., An, F., Fujita, Y., …Chen, L., Mattausch, H.J.， Low-power coprocessor for Haar-like feature extraction with pixel-based pipelined architecture， Japanese Journal of Applied Physics, 2017, 56(4), 04CF06 Zhang, X., An, F., Nakashima, I., …Ishii, I., Mattausch, H.J., A hardware-oriented histogram of oriented gradients algorithm and its VLSI implementation, Japanese Journal of Applied Physics, 2017, 56(4), 04CF01 Guan, J., An, F., Zhang, X., Chen, L., Mattausch, H.J., Real-time straight-line detection for XGA-size videos by hough transform with parallelized voting procedures, Sensors (Switzerland), 2017, 17(2), 270 Fujita, Y., An, F., Luo, A., …Chen, L., Mattausch, H.J., Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, 2017, pp. 611–612, 7804044 Pang, W., Huang, H., An, F., Yu, H., Low-power and real-Time computer vision on-chip, ISOCC 2016 – International SoC Design Conference: Smart SoC for Intelligent Things, 2016, pp. 43–44, 7799731 An, F., Zhang, X., Chen, L., Mattausch, H.J., A Memory-Based Modular Architecture for SOM and LVQ with Dynamic Configuration, IEEE Transactions on Multi-Scale Computing Systems, 2016, 2(4), pp. 234–241, 7604135 An, F., Mihara, K., Yamasaki, S., Chen, L., Mattausch, H.J., K-nearest neighbor associative memory with reconfigurable word-parallel architecture, Journal of Semiconductor Technology and Science, 2016, 16(4), pp. 405–414 An, F., Zhang, X., Chen, L., Mattausch, H.J., Dynamically reconfigurable system for LVQ-based on-chip learning and recognition, Proceedings – IEEE International Symposium on Circuits and Systems, 2016, 2016-July, pp. 1338–1341, 7527496 Zhang, X., An, F., Chen, L., Mattausch, H.J., Reconfigurable VLSI implementation for learning vector quantization with on-chip learning circuit, Japanese Journal of Applied Physics, 2016, 55(4), 04EF02 An, F., Mihara, K., Yamasaki, S., Chen, L., Mattausch, H.J., Highly flexible nearest-neighbor-search associative memory with integrated k nearest neighbor classifier, configurable parallelism and dual-storage space, Japanese Journal of Applied Physics, 2016, 55(4), 04EF10 An, F., Chen, L., Akazawa, T., Yamasaki, S., Mattausch, H.J., k nearest neighbor classification coprocessor with weighted clock-mapping-based searching, IEICE Transactions on Electronics, 2016, E99C(3), pp. 397–403 An, F., Mihara, K., Yamasaki, S., Chen, L., Mattausch, H.J., Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors, 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 – Proceedings, 2016, 7387456 An, F., Akazawa, T., Yamasaki, S., Chen, L., Mattausch, H.J., VLSI realization of learning vector quantization with hardware/software co-design for different applications, Japanese Journal of Applied Physics, 2015, 54(4), 04DE05 An, F., Akazawa, T., Yamazaki, S., Chen, L., Mattausch, H.J., LVQ neural network SoC adaptable to different on-chip learning and recognition applications, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, 2015, 2015-February(February), pp. 623–626, 7032858 An, F., Akazawa, T., Yamazaki, S., Chen, L., Mattausch, H.J., A coprocessor for clock-mapping-based nearest Euclidean distance search with feature vector dimension adaptability, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, 2014, 6946096 Wicaksono, I.B., An, F., Mattausch, H.J., Memory-based hardware-accelerated system for high-speed human detection, Advanced Robotics, 2014, 28(5), pp. 317–327 An, F., Chen, L., Mattausch, H.J., A SoPC architecture for nearest-neighbor based learning and recognition, 2014 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2014, 2014, pp. 147–152, 7024442 Wicaksono, I.B., An, F., Mattausch, H.J., A Hardware-Accelerated Reduced Dimensionality Multi-Prototype Learning and Recognition System with complementary classifiers, Proceedings of the 2013 IEEE Conference on Cybernetics and Intelligent Systems, CIS 2013, 2013, pp. 1–6, 6751569 An, F., Mattausch, H.J., K-means clustering algorithm for multimedia applications with flexible HW/SW co-design, Journal of Systems Architecture, 2013, 59(3), pp. 155–164 An, F., Mattausch, H.J., Cluster-based prototype learning system for multiple applications with flexible HW/SW codesign, Parallel and Distributed Computing, Applications and Technologies, PDCAT Proceedings, 2012, pp. 416–419, 6589314 Wicaksono, I.B., An, F., Mattausch, H.J., Human recognition with a hardware-accelerated multi-prototype learning and classification system, 2012 IEEE International Conference on Robotics and Biomimetics, ROBIO 2012 – Conference Digest, 2012, pp. 1507–1512, 6491182 An, F., Koide, T., Mattausch, H.J., A K-means-based multi-prototype high-speed learning system with FPGA-implemented coprocessor for 1-NN searching, IEICE Transactions on Information and Systems, 2012, E95-D(9), pp. 2327–2338 An, F., Mattausch, H.J., Koide, T., Real-time hybrid learning and recognition system with software-hardware cooperation, 2011 IEEE International Conference on Robotics and Biomimetics, ROBIO 2011, 2011, pp. 2505–2510, 6181681 专利： 识别系统，日本，2017-08-10 LVQ神经网络，日本，2019-7-14 新闻动态 更多新闻 南方科技大学安丰伟教授做客华中科技大学光电信息学术讲座 2019-10-30 中国石油大学邀请安丰伟副教授做客“名师有约”学术论坛 2019-10-30 团队成员 查看更多 PrevNext UpDown 加入团队 查看更多 联系我们 联系地址 广东省深圳市南山区南方科技大学第二科研楼329 办公电话 0755-88015992 电子邮箱 anfw@sustech.edu.cn