潘权
时间:2024-04-06 22:57 来源: 作者: 点击:次
教师主页 团队成员 科研项目 研究领域 学术成果 教学 科研分享 新闻动态 疼痛医学中心 成果介绍 软件 毕业去向 加入我们 联系我们 潘权 ResearcherID 长聘副教授/研究员 深港微电子学院 潘权博士，中国科学技术大学电子科学与技术专业学士，香港科技大学电子及计算机工程学专业博士。2005年到2009年在北京时代民芯科技有限公司担任射频芯片工程师。2014年到2018年在美国硅谷高速硬件创业公司eTopus Technology Inc. 担任高级主管工程师。主要研究工作集中在高速模拟/射频集成电路设计，主要包括：Wireline/Wireless高速通信集成电路、光通信集成电路、Serdes／clock and data recovery（CDR）电路、低噪声放大器/频率综合器、硅光互连研究。作为课题负责人不仅在国际主流会议／期刊上发表70多篇高水平学术论文，同时有超过8年丰富的国内外工作经验，包括4年硅谷业界最前沿的工作经验。入选国家领军人才，教育部特聘教授（青年），IEEE电路系统协会杰出青年作者奖，“珠江人才计划”引进高层次人才项目-青年拔尖人才，深圳海外高层次人才，南方科技大学校长青年科研奖，南方科技大学优秀教学奖，南方科技大学优秀书院导师奖。 个人简介 潘权博士，主要研究工作集中在高速模拟/射频集成电路设计，主要包括：Wireline/Wireless高速通信集成电路（接收机／发射机）、Serdes／clock and data recovery（CDR）电路、低噪声放大器/频率综合器、GaN集成电路、硅光互连研究。课题负责人不仅在国际主流会议／期刊上发表多篇高水平学术论文，同时有超过8年丰富的国内外工作经验，包括4年硅谷业界最前沿的工作经验。 科研工作经历 2022-至今 南方科技大学，长聘副教授/研究员（提前晋升） 2018-2022 南方科技大学，助理教授/副研究员 2014-2018 美国硅谷高速硬件创业公司eTopus Tech. Inc.，高级主管工程师 2005-2009 北京时代民芯科技有限公司，射频电路工程师 教育背景 2014 香港科技大学电子及计算机工程学系，博士学位 2005 中国科学技术大学电子科学与技术系，学士学位 主要荣誉 2019 “珠江人才计划”引进高层次人才项目-青年拔尖人才 2017 杰出青年作者奖, IEEE电路系统协会 2014 创新奖，第四届香港科大百万创业大赛 研究领域 高速光通信集成电路 Serdes/CDR电路 模拟/射频集成电路 硅光互连研究 GaN集成电路设计 学术任职 现担任以下期刊的审稿人： IEEE Journal of Solid-State Circuits IEEE Transactions on Microwave Theory and Techniques IEEE Transactions on Circuits and Systems I/II IEEE Photonics Technology Letter IEEE Journal of Lightwave Technology IEEE Transactions on Very Large Scale Integration (VLSI) Systems 现担任以下项目的评审人： 国家自然科学基金面上项目通讯评审 广东省自然科学基金项目评审 深圳市科创委员会项目评审 指导研究生和本科生成果 欢迎基础扎实，成绩好的同学加入我们团队，从事前沿芯片设计！ 强调理论分析能力、解决问题能力、个人综合能力的全面提升，成为具有国际视野的芯片设计师和未来的领导者！ 指导学生奖项 § 2023年，本科毕业生冯硕，虞新旦，詹东深，张睿贤，贾正哲，南方科技大学优秀本科毕业论文 § 2023年，本科毕业生詹东深，张睿贤，贾正哲，南方科技大学工学院综合设计二等奖 § 2022年，硕士研究生肖文博，南方科技大学优秀硕士学位论文 § 2022年，本科毕业生王磊明，南方科技大学优秀本科毕业论文 § 2021年，本科毕业生丘璋，朱思强，徐东藩，范怡然，周文韬，蔡平易，南方科技大学优秀本科毕业论文 § 2021年，本科毕业生丘璋，朱思强，徐东藩，南方科技大学工学院综合设计二等奖 § 2021年，本科毕业生范怡然，蔡平易，樊昕，南方科技大学工学院综合设计三等奖 § 2020年，硕士研究生胡俊峰，南方科技大学第二届工程硕士毕业成果一等奖 § 2020年，本科毕业生朱俊桦，钟宇昕，南方科技大学优秀本科毕业论文 § 2020年，本科毕业生李正浩，唐敏哲，樊泰扬，陆煜晨，南方科技大学工学院综合设计一等奖 个人简介 研究领域 光通信集成电路, Wireline/Serdes/TIA/CDR电路 模拟/射频集成电路，5G/毫米波集成电路设计 芯片级和板级EMI和噪声分析,高性能版图优化分析 硅光互连研究 研究方向介绍： 每年我都会收到很多学生的邮件，报考课题组的研究生和申请科研助理。但很多学生并不清楚自己感兴趣的研究领域。因此，我觉得有必要分享一些个人的见解，帮助学生们了解我们团队的研究方向。 从2005年到2009年，我从事的是无线射频收发机的产品开发，以频率综合器、低噪声放大器、混频器等IC为主。2009年到2014年进入港科大读博时，经过慎重选择，开始进入光通信/有线通信收发机领域的研究，具体的来说，是高性能信号链路芯片的研究。光电芯片的研究是最近十五年的非常重要的一个研究方向，在国内外都是非常热门和重要的研究领域，主要包括跨阻放大器、线性均衡器、前馈均衡器、时钟数据恢复电路、数模/模数转换器、各类驱动器芯片和锁相环电路。从2014年到2018年，机缘巧合进入一家硅谷创业公司，继续从事本领域的芯片研发。2018年后，加入南科大，成立独立的科研实验室。目前我们团队已在多个先进工艺节点上实现完整的光通信/有线通信集成电路信号链路芯片的研究和开发。本团队重视下一代高性能通信链路芯片的创新，希望新加入的学生志存高远，能立志为国家在本领域的技术突破做出一些贡献。 教学 主讲课程：模拟集成电路设计（本科）,射频通信集成电路与系统设计（研究生） 参讲课程：暂无 指导学生奖项： § 2023年，本科毕业生冯硕，虞新旦，詹东深，张睿贤，贾正哲，南方科技大学优秀本科毕业论文（组内2023届7位毕业本科生中有5人获得该奖项） § 2023年，本科毕业生詹东深，张睿贤，贾正哲，南方科技大学工学院综合设计二等奖 § 2022年，硕士研究生肖文博，南方科技大学优秀硕士学位论文 § 2022年，本科毕业生王磊明，南方科技大学优秀本科毕业论文 § 2021年，本科毕业生丘璋，朱思强，徐东藩，范怡然，周文韬，蔡平易，南方科技大学优秀本科毕业论文 § 2021年，本科毕业生丘璋，朱思强，徐东藩，南方科技大学工学院综合设计二等奖 § 2021年，本科毕业生范怡然，蔡平易，樊昕，南方科技大学工学院综合设计三等奖 § 2020年，硕士研究生胡俊峰，南方科技大学第二届工程硕士毕业成果一等奖 § 2020年，本科毕业生朱俊桦，钟宇昕，南方科技大学优秀本科毕业论文 § 2020年，本科毕业生李正浩，唐敏哲，樊泰扬，陆煜晨，南方科技大学工学院综合设计一等奖 欢迎基础扎实，成绩好的同学加入我们团队，从事前沿芯片设计！ 强调理论分析能力、解决问题能力、个人综合能力的全面提升，成为具有国际视野的芯片设计师和未来的领导者！ 学术成果 查看更多 研究成果主要发表在IEEE学术期刊及相关会议上，代表文章有： Journal Papers [J24] D. Xu, Y. Zhang, X. Luo, Z. Li, and Q. Pan*, “A 0.96–0.9-V Fully Integrated FVF LDO With Two-Stage Cross-Coupled Error Amplifier,” IEEE Transactions on Circuits and Systems Ⅱ, vol. 70, no. 10, pp. 3757-3761, Oct. 2023. [J23] J. Yang, Q. Pan*, J. Yin, Pui-In Mak, “A 2.0-to-7.4 GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS,” IEEE Transactions on Microwave Theory and Techniques, vol. 71, no. 8, pp. 3596-3604, Aug. 2023. [J22] X. Gui, R. Tang, K. Li, K. Wang, D. Li, Q. Pan, Li Geng, “A CMOS Slew-rate Controlled Output Driver With Low Process, Voltage and Temperature Variations Using a Dual-path Signal-superposition Technique,” IET Circuits Devices Syst., vol. 17, no. 1, 1– 16, 2022. [J21] Q. Jiang, Q. Pan*, “Analysis and Design of Tuning-less mm-Wave Injection-Locked Frequency Dividers with Wide Locking Range Using 8th-Order Transformer-Based Resonator in 40 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 57, no. 9, pp. 2812-2828, Sept. 2022. [J20] Q. Pan*, X. Luo, Z. Li, Z. Jia, F. Chen, C. P. Yue, “A 26-Gb/s CMOS Optical Receiver with a Reference-Less CDR in 65-nm CMOS,” Journal of Semiconductors(JOS), vol. 43, no.7, Mar. 2022. [J19] W. Xiao, Q. Huang, H. Mosalam, C. Zhan, Z. Li, and Q. Pan*, “A 6.15-10.9 Gb/s 0.58 pJ/bit Reference-Less Half-Rate Clock and Data Recovery with ‘Phase Reset’ Scheme,” IEEE Transactions on Circuits and Systems I, Reg. Papers, vol. 69, no. 2, pp. 634-644, Feb. 2022. [J18] J. Wang, X. Chen, R. Bai, and P. Y. Chiang, Q. Pan*, “A 4x10Gb/s Adaptive Optical Receiver Utilizing Current-Reuse and Crosstalk-Remove,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 12, pp. 2110-2118, Dec. 2021. [J17] Q. Pan*, X. Luo, “A 58-dBΩ 20-Gb/s inverter-based cascode transimpedance amplifier for optical communications,” Journal of Semiconductors(JOS), 2021. [J16] H. Mosalam, Q. Pan*, “A 57–100 GHz 0.13 μm SiGe power amplifier with high output power and efficiency,” Microeletronics Journal, 2021. [J15] J. Zhu, Q. Jiang, H. Mosalam, C. Zhan, Q. Pan*, “A 19-48.3-GHz 6th-order Transformer Based Injection locked Frequency Divider with 87.1% Locking Range in 40-nm CMOS,” IEEE Transactions on Circuits and Systems II: Express Briefs, 2021. [J14] H. Mosalam, W. Xiao, X. Gui, D. Li, Q. Pan*, “A 54-68 GHz Power Amplifier with Improved Linearity and Efficiency in 40 nm CMOS,” IEEE Transactions on Circuits and System II: Express Briefs, 2021. [J13] H. Mosalam, W. Xiao, Q. Pan*, “A 50-82 GHz Broadband Cascode-Based Power Amlifier in 40 nm CMOS,” International Journal of Electronics and Communications, 2021. [J12] Z. Li, M. Tang, T. Fan, Q. Pan*, “A 56-Gb/s PAM4 Receiver Analog Front-End with Fixed Peaking Frequency and Bandwidth in 40-nm CMOS,” IEEE Transactions On Circuits And Systems II: Express Briefs, 2021. [J11] Q. Huang, C. Zhan*, L. Wang, Z. Li, Q. Pan*, “A -40 ∘C to 120 ∘C, 169 ppm/∘C Nano-Ampere CMOS Current Reference,” IEEE Transactions On Circuits And Systems II: Express Briefs, issue. 67(9), pp. 1494-1498, 2020. [J10] Q.Pan*,L. Wang, X. Luo, and C. P.Yue, “A Low-Power PAM4 Receiver with an Adaptive Variable-Gain Rectifier Based Decoder,”IEEE Transactions on Very Large Scale Integration (VLSI) Systems, issue. 28(10), pp. 2099-2108, 2020. [J09] J. Hu, Z. Zhang , Q. Pan*,”A 15-Gb/s 0.0037-mm2 0.019-pJ/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator,”IEEE Transactions On Circuits And Systems II: Express Briefs, issue. 67(9), pp. 1499-1503, 2020. [J08] Q. Pan*, Y. Wang, and C. P. Yue, “A 42-dB Omega~25 -Gb/s CMOS Transimpedance Amplifier with Multiple-Peaking Scheme for Optical Communications,”IEEE Transactions On Circuits And Systems II: Express Briefs,issue. 67(1),pp. 72−76, 2020. [J07]J. Wang, Q. Pan* and Y. Qin, “A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 10, pp. 1698-1702, 2019. [J06] Y. Wang, D. Luo, Q. Pan*, L. Jing, Z. Li, and C. P. Yue, “A 60-GHz 4-Gb/s Fully Integrated NRZ-to-QPSK Fiber-Wireless Modulator,” IEEE Transactions of Circuits and Systems−I (TCAS-I), vol. 64, issue. 3, pp. 653−663, Mar. 2017. [J05] Q. Pan*, Y. Wang, Y. Lu, and C. P. Yue, “An 18-Gb/s Fully Integrated Optical Receiver with Adaptive Cascaded Equalizer,” IEEE Journal of Selected Topics in Quantum Electronics (JSTQE), vol. 22, no. 6, Nov./Dec. 2016. (Top-level optical/electrical journal. CMOS optical receiver research including both optical device and electrical circuits) [J04] Y. Lu, Y. Wang, Q. Pan*, C. P. Yue, and W. H. Ki, “A Fully-Integrated Low-Dropout Regulator with Ultra-Fast Transient Response and Full-Spectrum Power Supply Rejection,”IEEE Transactions of Circuits and Systems−I (TCAS-I), vol. 63, no. 3, pp. 707−716, Mar. 2015. [J03] Q. Pan*, Y. Wang, Z. Hou, L. Sun, Y. Lu, L. Wu, W. H. Ki, P. Chiang, and C. P. Yue, “A 30-Gb/s 1.37-pJ/b CMOS Receiver for Optical Interconnects,”IEEE Journal of Lightwave Technology (JLT), vol. 33, no. 4, pp. 778−786, Feb. 2015. (Top-level optical journal. High-speed CMOS optical circuits research) On/Before 2014: [J02] L. Sun, Q. Pan*, K. C. Wang, and C. P. Yue, “A 26-28-Gb/s clock and data recovery circuit with embedded equalizer in 65-nm CMOS,” IEEE Transactions of Circuits and Systems−I (TCAS-I), vol. 61, no. 7, pp. 2139−2149, Jul. 2014. [J01] Q. Pan*, Z. Hou, Y. Li, A. W. Poon, and C. P. Yue, “A 0.5-V P-Well/Deep N-Well photodetector in 65-nm CMOS for monolithic 850-nm optical receivers,”IEEE Photonics Technology Letters (PTL), vol. 26, no. 12, pp. 1184−1187, Jun. 2014. (Top-level optical journal. Optical device research) Conference Papers [C43] H. Wu, W. Wu, L. Zhong, X. Chen, Y. Zhang, X. Luo, D. Xu, X. Yu, Q. Pan*, “A 128Gb/s PAM-4 Transmitter with Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28nm CMOS,” in 2024 IEEE Custom Integrated Circuits Conf. (CICC), Denver, CO, USA, 2024. (Accepted). [C42] J. Yang, T. Xu, X. Meng, Z. Li, P-I. Mak, R. P. Martins, Q. Pan*, “A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS,” in 2024 IEEE Custom Integrated Circuits Conf. (CICC), Denver, CO, USA, 2024. (Accepted). [C41] F. Chen, C. P. Yue, Q. Pan*, “A 56-Gbaud 7.3-Vppd Linear Modulator Transmitter with AMUX-based Re-configurable FFE and Dynamic Triple-stacked Driver in 130-nm SiGe BiCMOS,” in 2024 IEEE Custom Integrated Circuits Conf. (CICC), Denver, CO, USA, 2024. (Accepted). [C40] X. Luo, X. You, H. Mosalam, H. Qiao, D. Xu, Z. Li, T. Fan, W. Zhou, H. Wu, L. Zhong, P. Y. Chiang, Q. Pan*, “A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Loss Compensation for 800GbE/1.6TbE,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, 2024, pp. 132-134. [C39] L. Zhong, H. Wu, Y. Zhang, X. Cheng, W. Wu, X. Luo, T. Fan, D. Xu, Q. Pan*, “A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, 2024, pp. 134-136. [C38] W. Wu, H. Wu, L. Zhong, X. Chen, X. Luo, D. Xu, Z. Li and Q. Pan*, “A 64Gb/s/pin PAM4 Single-Ended Transmitter with Merged Pre-Emphasis Capacitive Peaking Crosstalk Cancellation for Memory Interfaces in 28nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, 2024, pp. 240-242. [C37] F. Chen, C. Zhang, L. Wang, Q. Pan* and C. P. Yue, “A 2.05-pJ/b 56-Gb/s PAM-4 VCSEL Transmitter with Piecewise Nonlinearity Compensation and Asymmetric Equalization in 40-nm CMOS,” in IEEE 49th European Solid State Circuits Conference (ESSCIRC), Lisbon, Portugal, 2023, pp. 373-376. [C36] H. Wu, W. Wu, L. Zhong, X. Cheng, X. Luo, Z. Li, D. Xu, and Q. Pan*, “A 2x24Gb/s Single-Ended Transceiver with Channel-Independent Encoder-Based Crosstalk Cancellation in 28nm CMOS,” in 2023 IEEE Asian Solid-State Circuits Conference(ASSCC), 2023. [C35] D. Zhou, H. Wang, D. Zhan, and Q. Pan*, “Transit-time Enhanced Silicon Photodetector with Lateral Interleaved P-well/N-well Junction in 28-nm CMOS Technology,” in European Conference on Optical Communications (ECOC), 2023. [C34] D. Xu, Y. Zhang, Z. Li, X. Luo, P. Cai, Q. Pan*, “A Fully-Integrated LDO with Two-Stage Cross-Coupled Error Amplifier for High-Speed Communications in 28-nm CMOS,” in IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, 2023, pp. 1-4. [C33] D. Zhan, L. Zhong, W. Zhou, Z. Yao, X. Luo, Y. Zhang, H. Wang, D. Zhou, and Q. Pan*, “A 28-Gb/s PAM-4 Fully-Integrated Optical Receiver with High-Speed Silicon Photodetector in 28-nm CMOS,” in IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), Hefei, China, 2023, pp. 192-193. [C32] S. Feng, F. Chen and Q. Pan*, “A Power-Efficient 4−Vppd 128-Gb/s PAM-4 Optical Modulator Driver with Merged BV Doubler Topology in 130-nm BiCMOS,” in 2023 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), Hefei, China, 2023, pp. 190-191. [C31] Wang, X. Luo, D. Xu, Z. Qiu, Y. Yan, Q. Pan*, “A 160-Gb/s 0.37-pJ/bit PAM4 Optical Receiver in 28-nm CMOS,” in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Shenzhen, China, 2022, pp. 333-336. [C30] S. Feng, F. Chen, Z. Li, W. Zhou, D. Xu, C. Chen, X. Liu, H. Wu, Q. Pan*, “A 4-Vppd 160-Gb/s PAM-4 Optical Modulator Driver with All-Pass Filter-Based Dynamic Bias and 2-Tap FFE in 130-nm BiCMOS,” 2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Shenzhen, China, 2022, pp. 1-5. [C29] Z. Jia, T. Fan, D. Xu, D. Zhan, L. Hu, Z. Zhang, Y. Wang, Q. Pan, “A 200-Gb/s PAM-4 Feedforward Linear Equalizer with Multiple-Peaking and Fixed Maximum Peaking Frequencies in 130nm SiGe BiCMOS“, 2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), Xi’an, China, pp. 104-105, 2022. [C28] L. Zhong, H. Wu, W. Wu, W. Xiao, X.Luo, D. Xu, X. Cheng, Z. Li, T. Fan, Q. Pan, “A 2×50 Gb/s Single-Ended MIMO PAM-4 Crosstalk Cancellation and Signal Reutilization Receiver in 28 nm CMOS,” European Solid-State Circuits Conference(ESSCIRC), 2022. [C27] X. Luo, X. You, J. Fu, Z. Li, L. Zhong, T. Fan, Z. Qiu, W. Xiao, Y. Chen, Q. Pan, “A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach Link,” European Solid-State Circuits Conference(ESSCIRC), 2022. [C26] S. Zhuo, L. Zhao, P. Chiang, Q. Pan, et al., “Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20W/Ch Transmitter, and a 128×128 SPAD Receiver with SNR-Based Pixel Binning and Resolution Upscaling,” IEEE custom Integrated Circuits Conference (CICC), 2022. [C25] Z. Qiu, X. Luo, Z. Li, S. Zhu, L. Wang, Z. Mao, X. Gui, D. Li, Q. Pan, “A 720-m Vpp 224-Gb/s PAM4 Optical Receiver with Multiple Peaking Techniques in 130-nm SiGe BiCMOS,” IEEE Asia Pacific Conference on Circuits and Systems(APCCAS), 2021. (Accepted) [C24] Q. Jiang and Q. Pan, ” Tuning-Less Injection-Locked Frequency Dividers with Wide Locking Range Utilizing 8th-Order Transformer-Based Resonator,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2021. [C23] D. Xu, Y. Kou, P. Lai, Z. Cheng, T. Y. Cheung, L. Moser, Y. Zhang, X. Liu, M. P. Lam, H. Jia, Q. Pan, W. H. Szeto, C. F. Tang, K. F. Mak, K. Sarfraz, T. Zhu, M. Kwan, E. Y. L. Au, C. Conroy, K. K. Chan, “A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm,” 2020 International Solid-State Circuit Conference(ISSCC).2021 [C22] D. Li, S. Gao, Y. Shi, X. Gui, N. Qi, Z. Li, Q. Pan, P. Chiang, L. Geng, “A 112-Gb/s PAM-4 Linear Optical Receiver in 130-nm SiGe BiCMOS,” 2020 IEEE International Symposium on Circuits and Systems (ISCAS).2020 [C21] D. Xu, Z. Qiu, X. Luo, X. You, W. Xiao, S. Zhu, M. Tang, Z. Li, Q. Pan, “Fully-Differential 100-Gb/s PAM4 Cross-Coupled Regulated Transimpedance Amplifier” 2020 IEEE International Conference on Integrated Circuits, Technologies and Applications（ICTA）.2020 [C20] J. Fu, P. Cai, X. Luo, X. You, L. Zhong, W. Xiao, F. L., Yao Li , Q. Pan, “A 224-Gb/s PAM4 High-Linearity, Energy-Efficiency Differential to Single-Ended Driver in 130-nm SiGe BiCMOS,” 2020 IEEE International Conference on Integrated Circuits, Technologies and Applications（ICTA）.2020 [C19] X. Wang, Y. Peng, Y. Zhang, T. Xia, Y. Wu, J. Wang, L. Wang, L. Song, L. Zhao, S. Zhuo, Q. Pan, Xuefeng Chen ,Patrick Yin Chiang and Rui Bai, “A 25Gb/s-PAM4 Optical Transceiver Chipset for 5G Optical Front-Haul”, 2020 Optical Fiber Communications Conference and Exhibition (OFC).2020 [C18] J. Hu, Z. Zhang, Q. Huang, J. Yang, M. Hu, Q. Jiang, Y. Guo, Q.Pan, “An 18-Gb/s 36×13-µm2 3.53-mW 2^7-1 PRBS Generator in 40-nm CMOS”, 2020 IEEE International Conference on Electronics, Information, and Communication (ICEIC), Barcelona, Spain, Jan. 2020 [C17] M. Tang, Z. Li, J. Hu, Q. Huang, N, Qi, H. Yu, Q. Pan, “A 56-Gb/s PAM4 Continuous-Time Linear Equalizer with Fixedin Peaking Frequency in 40-nm CMOS,” 2019 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), Cheng’du, China, Nov. 2019. [C16] S. Hu, T. Yao, T. Yao, B. Yin, C. Song, L. Zhao, J. Wang, R. Bai, X. Wang, T. Xia, Y. Peng, B. Yao, Y. Li, Q. Pan, Nan Qi, X. Chen, P. Y. Chiang, “A 50Gb/s PAM-4 Retimer-embedded VCSEL Driver with Asymmetric Pulsed Pre-emphasis in 40nm CMOS”, Optical Fiber Communication Conference and Exhibit. Technical Digest (OFC), Mar. 2019. [C15] Z. Li, M. Tang, Y. Guo, Q. Huang and Q. Pan, “A 56-Gb/s PAM4 Variable Gain Amplifier in 40-nm CMOS Technology,” in 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Xi’an, China, 2019, pp. 1―3. [C14] Y. Guo and Q. Pan, “A PAM-4 80-Gb/S Variable-Gain Transimpedance Amplifier in 40-nm CMOS Technology,” in IEEE International Conference on Integrated Circuits,Technologies and Applications, Nov. 2018. [C13] G. Zhu, Q. Pan, J. Zhuang, C. Zhi, and C. P. Yue, “A Low-Power PAM4 Receiver Using 1/4-Rate Sampling Decoder with Adaptive Variable-Gain Rectification,” in 2017 IEEE Asian Solid-State Circuits Conf., Nov. 2017. [C12] Y. Wang, D. Luo, Q. Pan, L. Jing, Z. Li, and C. P. Yue, “A 60GHz 4Gb/s Fully Integrated NRZ-to-QPSK Modulator SoC for Backhaul Links in Fiber-Wireless Networks,” in Proc. European Solid-State Circuits Conf., Sep. 2015. On/Before 2014: [C11] Q. Pan, Y. Wang, Z. Hou, L. Sun, L. Wu, W. H. Ki, P. Chiang, and C. P. Yue, “A 41-mW 30-Gb/s CMOS Optical Receiver with Digitally-Tunable Cascaded Equalization,” in Proc. European Solid-State Circuits Conf., Sep. 2014. (Top-level circuits conference. High-speed CMOS optical circuits) [C10] Q. Pan, L. Sun, and C. P. Yue, “Differential Stacked Spiral Inductor and Transistor Layout Designs for Broadband High-Speed Circuits,” in IEEE Radio Frequency Integration Technology, Aug. 2014. (International device/circuits conference. RF inductor device research) [C09] Q. Pan, Z. Hou, Y. Wang, Y. Lu, W. H. Ki, K. C. Wang, and C. P. Yue, “A 48-mW 18-Gb/s Fully Integrated CMOS Optical Receiver with Photodetector and Adaptive Equalizer,” in Symp. VLSI Circuits Dig. Tech. Papers, pp. 116−117, Jun. 2014. (Top-level circuits conference. High-speed CMOS optical system with both device and circuits research) [C08] Y. Wang, Y. Lu, Q. Pan, Z. Hou, L. Wu, W. H. Ki, and C. P. Yue, “A 3-mW 25-Gb/s CMOS transimpedance amplifier with fully integrated low-dropout regulator for 100GbE systems,” in IEEE Radio Frequency Integrated Circuits Symp., pp. 275−278, Jun. 2014. [C07] Z. Hou, Q. Pan, Y. Wang, L. Wu, and C. P. Yue, “A 23-mW 30-Gb/s digitally programmable limiting amplifier for 100GbE optical receivers,” in IEEE Radio Frequency Integrated Circuits Symp., pp. 279−282, Jun. 2014. [C06] Q. Pan, Z. Hou, Y. Wang, and C. P. Yue, “A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical receivers,” in IEEE 10th International Conference on ASIC, Oct. 2013. (International device-level conference. Optical photodetector device research) [C05] L. Sun, Q. Pan, K. C. Wang, and C. P. Yue, “A 25-28 Gbps clock and data recovery system with embedded equalization in 65-nm CMOS,” in Inter. Conference on Solid-State and Integrated Circuit Tech., Oct. 2012. [C04] Q. Pan, T. J. Yeh, C. Jou, F. L. Hsueh, H. Luong, and C. P. Yue, “A performance study of layout and Vt options for low noise amplifier design in 65-nm CMOS,” in IEEE Radio Frequency Integrated Circuits Symp., pp. 535−538, Jun. 2012. (Top-level circuits conference. High-speed CMOS LNA circuits with device research for TSMC project – transistor study) [C03] D. Zhang, Z. Wen, W. Li, Q. Pan, “A Large Gain Variable Range, Wide Band width Analog AGC Circuitry for a CMOS GPS Receiver”, Robot World 2008, Seoul, Korea, Oct. 2008. [C02] Q. Pan, Z. Wen, and W. Li, “A 1.57-GHz low-power low-phase-noise quadrature LC-VCO,” in WCECS 2008, pp. 192‒195, Oct. 2008. [C01] Q. Pan, Z. Wen, Y. Zhang, and B. Bi, “Phase Noise and Power Optimization of a 2-GHz Differential CMOS LC VCO,” in IEEE Radio Frequency Integration Technology, pp. 258‒261, Aug. 2007. 新闻动态 更多新闻 潘权课题组三篇论文被ISSCC录用 2024-03-06 祝贺潘权课题组三篇论文被顶级会议CICC 2024接收 2024-03-06 祝贺潘权课题组三篇论文被顶级会议ISSCC 2024接收 2023-10-17 团队成员 查看更多 PrevNext UpDown 加入团队 南方科技大学微电子学院 模拟/通信集成电路设计方向 招聘博士后/研究助理教授/研究副教授 招收博士生/硕士生/研究助理 课题组介绍：本课题组的主要研究方向是：通信集成电路（接收机／发射机）、Serdes／clock and data recovery（CDR）电路、毫米波集成电路、硅光互连研究。拟招聘博士生/硕士生/研究助理多名。同时，团队正在招收高速通信芯片设计领域博士后，研究助理教授，研究副教授，年薪35-60万。特别优秀者可以面议。感兴趣的学者可将详细的个人简历，含学习、工作和科研的经历，主要科研成果，及其他可以证明工作能力的材料，投送到老师邮箱。（有效期到2023年12月） 应聘要求研究领域1) Wireline/Optical通信集成电路设计（transceiver）, TIA/CTLE/DFE/ FFE/LA/Driver, Serdes/clock and data recovery circuits;2) Wireless射频集成电路设计，LNA/mixer/VGA/frequency synthesizer/PA，毫米波IC设计。3）硅光互连研究 博士后岗位1) 已取得或即将取得博士学历学位；2) 热爱科学研究、勤奋努力、具有主动性、强烈的进取心；3) 能够熟练使用英文进行交流，能够完成研究论文的撰写；4) 在国内外刊物以第一作者身份发表过较高水平科研论文；5) 具有模拟／射频／高速电路设计经验经历者优先考虑。 研究助理岗位1) 取得或将取得相关专业的学士以上学位；2) 具有良好的英文读，写，说能力和计算机操作能力；3） 具有模拟／射频／高速电路设计经验经历者优先考虑。 岗位待遇博士后待遇 1）参照《南科大博士后管理办法》及深圳市相关人才引进条例，年薪30万元（含市政补贴税后18万元/年）；提供2800元/月住房补贴（如户口迁往深圳，还可额外获得政府免税住房补贴3万元），餐补220元/月。优秀者可申请校长卓越博士后，年薪35万/年。2）享受正式教职工待遇（（含伙食补贴、节日补贴、工会福利、计生补贴、体检等等）；3）可作为负责人申请博士后科学基金、国家自然科学基金及省、市各级课题；4）出站留深工作满3年，符合深圳市后备级条件的可获160万元的住房补贴和可申请30万元RMB科研启动经费；5）海外博士符合条件者可以申请深圳市孔雀计划160万住房补贴；6）学校为每位博士后提供每两年2.5万元的学术交流资助。 科研助理待遇1) 薪酬按学校相关规定定薪，月薪6000-13000元/月，视个人情况可向上浮动；2) 大学规定的各种补助，年度考核奖金；3) 落户深圳并帮助申请深圳市各类人才补助；4） 有意攻读博士学位者也可先以研究助理身份加入课题组积累科研经验，之后可推荐攻读境内外博士生。 博士生硕士生招聘：硕士生正常报考南科大本校学位点。（读硕期间生活补助：5万/年） 有意攻读博士学位的同学和科研人员，可选择本校博士学位，也可被推荐攻读联合培养博士生。联合培养学校包括以下著名/知名大学（香港科大、香港大学、新加坡国立、香港浸会大学、利兹大学、伯明翰大学、华威大学、东英吉利亚大学、澳门大学、美国天普大学等）。培养模式为2年国外/境外+2年南科大。本课题组目前主要的联合培养学校为澳门大学，香港科技大学和新加坡国立大学。博士学位为对方学校颁发。（读博期间生活补助：10万/年） 欢迎对混合／模拟／射频IC设计感兴趣的同学和科研人员加盟。同时欢迎来自国内外一流大学的访问学者和交流学生。 申请材料详细的个人简历，含学习、工作和科研的经历，主要科研成果（如论文论著、成果证书或奖励），及其他可以证明工作能力的材料。（邮件标题注明:毕业学校+姓名+应聘职位）（本招聘信息长期有效）欢迎有意者投简历到邮箱：panq@sustech.edu.cn 查看更多 联系我们 联系地址 深圳市南山区学苑大道1088号台州楼210 办公电话 电子邮箱 panq@sustech.edu.cn |