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个人简介：Personal Profile 个人简介    靳刚，男，博士，副教授，硕士生导师。    在西安电子科技大学分别获得学士、硕士和博士学位，2011年6月至8月在比利时欧洲校际微电子中心（Interuniversity MicroElectronics Centre, IMEC）和鲁汶大学作访问学者，2017年9月至2018年9月在美国德克萨斯大学（University of Texas at Austin, UT）作访问学者。    2004年3月留校任教，研究方向为数模混合与射频集成电路设计与生物微电子，长期从事数模混合芯片、射频芯片、通信基带芯片、生物医疗芯片等方向的芯片研究和设计工作。主持或参与国家科技重大专项、部委科技项目、国家自然科学基金项目、陕西省重点研发计划等各类国家及省部级项目10余项，包括卫星定位导航芯片、通信类基带芯片、数字-时间转换器芯片和纳米孔DNA测序阵列芯片等核心芯片研发。发表学术论文十余篇，全部被SCI或EI检索，担任多个学术期刊审稿人，申请国家发明专利十余项。研究方向生物微电子    脑机接口芯片研究、纳米孔DNA测序阵列芯片研究数模混合集成电路设计    高速数据接口设计、锁相环电路研究与设计、数字化模拟电路研究与设计射频与通信集成电路设计    射频收发机芯片设计、通信类基带芯片设计验证主讲课程本科生课程：《数字逻辑与集成设计》、《数字集成电路》研究生课程：《VLSI系统设计》、《数字集成系统设计》招生要求：学习能力强、踏实刻苦、具有创新精神Chip GalleryGlobal Navigation Satellite System (GNSS) Receiver RF Front-end Chip 卫星导航接收机射频前端芯片        [1]    Y. Yin, Y. Zhuang, G. Jin*, X. Qi, and X. Xiang, “A novel CMOS active polyphase filter with wideband and low-power for GNSS receiver,” IEICE Electronics Express, 13(7), 2016.(SCI: 000377762500013, EI: 20161602262039)[2]    Jin Gang*, Zhuang Yiqi; Yin Yue, Cui Miao, A digitally controlled AGC loop circuitry for GNSS receiver chip with a binary weighted accurate dB-linear PGA, Journal of Semiconductors, 2015, 36(3): 035004-7 (EI:20151300687710)[3]    Jin Gang*, Zhuang Yiqi, Cui Miao, Yin Yue, Li Cong, Xiang Xin, A stable and two-step settling digital controlled AGC loop for GNSS receiver, IEICE Electronics Express, 2014, 11(19). (SCI:000344926500008, EI:20144200106642)[4]    Yin Yue, Zhuang Yiqi, Jin, Gang*, Fan Xiaoqiang, Qi Xiaofei, Xiang Xin, A 48-dB precise decibel linear programmable gain amplifier for GNSS receivers, IEICE Electronics Express, 2014, 11(21):1-6 (SCI:000346400500008, EI:20144600194670)[5]    Y. Yin, Y. Zhuang, G. Jin*, X. Qi, and X. Xiang, “A novel CMOS active polyphase filter with wideband and low-power for GNSS receiver,” IEICE Electronics Express, 13(7), 2016. (SCI: 000377762500013, EI: 20161602262039)[6]    Li Zhenrong, Zhuang Yiqi, Li Bing, Jin Gang, A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider, Journal of Semiconductors, 2011, 32 (7): 075008-7. (EI: 20113014182416)[7]    Li Bing, Zhuang Yiqi, Long Qiang, Jin Zhao, Li Zhenrong, Jin Gang, Design of a 0.18 m CMOS multi-band compatible low power GNSS receiver RF frontend, Journal of Semiconductors, 2011, 32(3), 035007-11 (EI:20111513903247)[8]    Li Zhenrong, Zhuang Yiqi, Li Bing, Jin Gang, Jin Zhao, A 2.4 GHz high-linearity low-phase-noise CMOS LC-VCO based on capacitance compensation, Journal of Semiconductors, 2010, 31(7), 075005-6[9]    Li Bing, Zhuang Yiqi, Li Zhenrong, Jin Gang, A 0.18 m cmos Dual-band low Power low Noise Amplifier for a Global Navigation Satellite System, Journal of Semiconductors, 2010, 31(12), 125001-7 (EI:20110313602705)Digital to Time Converter(DTC)/Digitally Controlled Oscillator(DCO) （全数字）时间数字转换器/数控振荡器       Nanopore DNA Sequencing Array Chip  纳米孔DNA测序阵列芯片      发明专利    一种基于非线性斜坡量化的纳米孔DNA测序电路发明专利    公开    CN202111546908.9发明专利    用于纳米孔基因测序的读出电路及半边共享读出阵列            授权    CN202110750091.0SEU-tolerant Pulse Flip-Flop Chip 抗辐照脉冲触发器验证样片            [1]    Hao Wu, Gang Jin* and Yiqi Zhuang, “Design and analysis of a SET tolerant single‑phase clocked double‑tail dynamic comparator”, Analog Integrated Circuits and Signal Processing, 2022.[2]    H. Wu, G. Jin*, Y. Zhuang, W. Cao, and L. Bai, “A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design,” IEICE Electronics Express, 18(17), 2021. (SCI: 000709406000004, EI: 20214010965552)